The semiconductor industry makes wide use of packaging substrates to hold and electrically interconnect integrated circuit (IC) die mounted within the packaging substrate. In some implementations the packaging substrates are configured to protect and secure the delicate IC die while enabling electrical connections with known external electrical interconnection socket formats. When used for low speed integrated circuits, these packaging substrates include standard ground planes for grounding the circuitry of integrated circuit die mounted in semiconductor packages. In typical implementations the IC die is grounded to a single ground plane (also referred to herein as a “Vss plane”) which is grounded to another system ground. For example, the package can be grounded by solder attachment to a mother board ground. Typically, a packaging substrate includes a BT (bismaleimide triazine) core having various metallization and solder mask layers to form the substrate. As is known to those having ordinary skill in the art other substrate materials can be used. For example, ceramic and other materials are also commonly employed. In one common implementation semiconductor die is attached to the substrate and electrically connected to various electrical connections of the substrate using, for example, wire-bonding techniques. The wire bonds and the die are typically encapsulated with a protective layer of encapsulant. Such packages and the methods of their construction are well known to persons having ordinary skill in the semiconductor packaging arts. Typically, the packages are then provided with a stiffener and a heat spreader to complete the packages.
FIG. 1 is a simplified schematic plan view of a portion of a standard PBGA (plastic ball grid array) package 100 configured in accordance with known prior art technologies. The depicted package 100 includes a circuit die 101 typically arranged on a die attach pad. A series of metallization structures are arranged about the die 101. In the depicted structure, a ground layer (Vss) 111 is arranged about the die 101. A core power layer (VDD core) 112 forms another metallization layer. VDD core 112 is typically connected with metal filled vias to underlying solder balls that are connected to a system power. Another input output (I/O) power layer (VDD I/O) 113 forms another metallization layer for connection to I/O power. Additionally, the package includes electrical contact “fingers” 114. Typically, metallization lines 115 electrically connect the fingers to vias (not shown) that connect with solder balls on the bottom of the substrate. In some configurations the fingers 114 are typically connected to the ground plane 111. The die 101 includes a series of bond pads 102 that are connected with the fingers 114, Vss 111 (ground), VDD core 112, VDD I/O 113 with wire bonds 103. In the depicted die 101 the high speed portions of the die and low speed portions of the die are electrically connected to the same ground plane Vss 111.
However, higher speed circuitry is being employed in the construction of modern IC's. Frequently, these newer IC's include both high speed and lower speed systems. This dichotomy presents a number of problems not solved by existing packaging substrates. As depicted above, existing packages generally include a single ground plane for all IC systems and grounds. When all systems operated at low frequencies or low serial data transfer rates this situation was not much of a problem. However, at highs speeds a number of problems begin to occur. For one, excessive noise generated by the high-speed circuitry interferes with the operation of the low-speed circuitry sharing the same ground plane. At high data rates this is a serious problem. Additionally, older packaging substrates developed with lower speed circuitry in mind are configured the I/O and ground contacts spaced more closely together for maximum electrical contact density. However, at high frequencies and data rates signal and ground lines that are too closely spaced exhibit large amounts of cross talk. Again with serious consequences. Additionally, at high system performance the problem of ground bounce is magnified. Solutions to these problems have been difficult to solve.
Combining low speed and high-speed grounds on the same ground plane has generated numerous problems. One approach tried in the prior art required that individual pins be used for separately grounding each high-speed ground connection. This has the undesirable property of using up a limited amount of pins to accommodate ground connections. It also increases the density of high-speed interconnections resulting in undesirable cross talk between all ground and I/O lines. Such commonly constructed packages have until recently provided satisfactory grounding for packaging substrates. Now, with increasing IC speeds and data transfer rates the traditional package format is increasingly proving be unsatisfactory. Accordingly, what is needed is a packaging design and approach that provides superior grounding properties enabling both high speed and low speed circuitry to be used in the same packaging substrate.